Status debugging bits
| MACRPES | When high this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state. |
| MACRFFCS | When high this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller. |
| MTLRFWCAS | When high this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. |
| MTLRFRCS | This field gives the state of the Rx FIFO read Controller: 2’b00: IDLE state.2’b01: Reading frame data.2’b10: Reading frame status (or timestamp).2’b11: Flushing the frame data and status. |
| MTLRFFLS | This field gives the status of the fill-level of the Rx FIFO: 2’b00: Rx FIFO Empty. 2’b01: Rx FIFO fill-level below flow-control deactivate threshold. 2’b10: Rx FIFO fill-level above flow-control activate threshold. 2’b11: Rx FIFO Full. |
| MACTPES | When high this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state. |
| MACTFCS | This field indicates the state of the MAC Transmit Frame Controller module: 2’b00: IDLE state. 2’b01: Waiting for status of previous frame or IFG or backoff period to be over. 2’b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2’b11: Transferring input frame for transmission. |
| MACTP | When high this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission. |
| MTLTFRCS | This field indicates the state of the Tx FIFO Read Controller: 2’b00: IDLE state. 2’b01: READ state (transferring data to the MAC transmitter). 2’b10: Waiting for TxStatus from the MAC transmitter. 2’b11: Writing the received TxStatus or flushing the Tx FIFO. |
| MTLTFWCS | When high this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. |
| MTLTFNES | When high this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission. |
| MTLTSFFS | When high this bit indicates that the MTL TxStatus FIFO is full. Therefore the MTL cannot accept any more frames for transmission. |